OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [asm/] - Rev 152

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
152 Updated to match the new/updated multiply instructions. Of course, this is
still hand optimized and not compiled--so it's not really a true and proper
test (yet), but ... it's what I have.		 dgisselq 2897d 23h /zipcpu/trunk/bench/asm/
151 Minor formatting change. dgisselq 2897d 23h /zipcpu/trunk/bench/asm/
150 Minor changes. dgisselq 2897d 23h /zipcpu/trunk/bench/asm/
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).		 dgisselq 3029d 01h /zipcpu/trunk/bench/asm/
74 Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files.		 dgisselq 3034d 04h /zipcpu/trunk/bench/asm/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3040d 09h /zipcpu/trunk/bench/asm/
57 Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there).		 dgisselq 3111d 11h /zipcpu/trunk/bench/asm/
50 Dhrystone benchmark updates--added the copyright notice. (Oops!) dgisselq 3121d 03h /zipcpu/trunk/bench/asm/
42 Oops -- forgot to add the stack. dgisselq 3121d 03h /zipcpu/trunk/bench/asm/
41 Assembly file for the Dhrystone benchmark added. dgisselq 3121d 03h /zipcpu/trunk/bench/asm/
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 3121d 03h /zipcpu/trunk/bench/asm/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3133d 12h /zipcpu/trunk/bench/asm/
12 Bunch of changes while trying to get a hello world program:
1. Right shifts by 32 or more now result in zero, or all of the top bit in the
case of ASRs.
2. zdump now properly includes addresses with dumped lines.
3. zparser now properly handles immediate values via the .DAT instruction.		 dgisselq 3187d 05h /zipcpu/trunk/bench/asm/
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)		 dgisselq 3187d 13h /zipcpu/trunk/bench/asm/
10 Here's the watchdog timer code, as well as some pictures of the register
set.		 dgisselq 3188d 02h /zipcpu/trunk/bench/asm/
2 An initial load. No promises of what works or not, but this is where the
project is at.		 dgisselq 3189d 03h /zipcpu/trunk/bench/asm/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.