| Rev |
Log message |
Author |
Age |
Path |
| 172 |
Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg(). |
dgisselq |
2781d 08h |
/zipcpu/trunk/bench |
| 168 |
An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them. |
dgisselq |
2842d 07h |
/zipcpu/trunk/bench |
| 159 |
Now supports building a simulator that can load ELF files, such as GCC and/or
binutils will produce. |
dgisselq |
2874d 03h |
/zipcpu/trunk/bench |
| 155 |
Improved debug trace quality, for finding bugs after the fact. |
dgisselq |
2874d 03h |
/zipcpu/trunk/bench |
| 154 |
Added timing checks on the busy and valid signals: either one of the two is
valid, or the whole is idle. |
dgisselq |
2874d 03h |
/zipcpu/trunk/bench |
| 152 |
Updated to match the new/updated multiply instructions. Of course, this is
still hand optimized and not compiled--so it's not really a true and proper
test (yet), but ... it's what I have. |
dgisselq |
2907d 02h |
/zipcpu/trunk/bench |
| 151 |
Minor formatting change. |
dgisselq |
2907d 02h |
/zipcpu/trunk/bench |
| 150 |
Minor changes. |
dgisselq |
2907d 02h |
/zipcpu/trunk/bench |
| 149 |
Updated the Makefile documentation and the all target. |
dgisselq |
2907d 02h |
/zipcpu/trunk/bench |
| 148 |
Minor changes to get LONG_MPY working, and adjust the documentation. |
dgisselq |
2907d 02h |
/zipcpu/trunk/bench |
| 147 |
Cleans up div_tb a bit, causing it to write SUCCESS out if successful and
abort if not. |
dgisselq |
2907d 02h |
/zipcpu/trunk/bench |
| 140 |
Minor changes, but fixes build of zippy_tb.cpp. |
dgisselq |
2910d 15h |
/zipcpu/trunk/bench |
| 134 |
Working updates, to keep this up to date with the RTL code. |
dgisselq |
2928d 03h |
/zipcpu/trunk/bench |
| 105 |
Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC. |
dgisselq |
2971d 12h |
/zipcpu/trunk/bench |
| 87 |
Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...) |
dgisselq |
3038d 04h |
/zipcpu/trunk/bench |
| 86 |
Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W). |
dgisselq |
3038d 04h |
/zipcpu/trunk/bench |
| 77 |
First check-in: the test bench for the divide instruction. |
dgisselq |
3043d 07h |
/zipcpu/trunk/bench |
| 76 |
The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions. |
dgisselq |
3043d 07h |
/zipcpu/trunk/bench |
| 75 |
Modified for VLIW instructions. |
dgisselq |
3043d 07h |
/zipcpu/trunk/bench |
| 74 |
Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files. |
dgisselq |
3043d 07h |
/zipcpu/trunk/bench |
| 69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3049d 12h |
/zipcpu/trunk/bench |
| 58 |
Added a rudimentary profiling support to the simulator. |
dgisselq |
3110d 12h |
/zipcpu/trunk/bench |
| 57 |
Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there). |
dgisselq |
3120d 14h |
/zipcpu/trunk/bench |
| 50 |
Dhrystone benchmark updates--added the copyright notice. (Oops!) |
dgisselq |
3130d 06h |
/zipcpu/trunk/bench |
| 43 |
Minor edits to the C++ testbench. |
dgisselq |
3130d 06h |
/zipcpu/trunk/bench |
| 42 |
Oops -- forgot to add the stack. |
dgisselq |
3130d 06h |
/zipcpu/trunk/bench |
| 41 |
Assembly file for the Dhrystone benchmark added. |
dgisselq |
3130d 06h |
/zipcpu/trunk/bench |
| 40 |
Quick update, updates the assembly for the new version of the assembler. |
dgisselq |
3130d 06h |
/zipcpu/trunk/bench |
| 39 |
Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked. |
dgisselq |
3133d 09h |
/zipcpu/trunk/bench |
| 36 |
*Lots* of changes to increase processing speed and remove pipeline stalls.
Removed the useless flash cache, replacing it with a proper DMA controller.
"make test" in the main directory now runs a test program in Verilator and
reports on the results. |
dgisselq |
3142d 15h |
/zipcpu/trunk/bench |
