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[/] [zipcpu/] [trunk/] [doc/] - Rev 156

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Rev Log message Author Age Path
153 Adds internal link functionality to the specification document format. dgisselq 2873d 04h /zipcpu/trunk/doc/
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.		 dgisselq 2912d 13h /zipcpu/trunk/doc/
107 Adding a missing file. dgisselq 2965d 05h /zipcpu/trunk/doc/
106 Updated to allow building without the sources for the graphics used in the
document.		 dgisselq 2965d 09h /zipcpu/trunk/doc/
92 Adjustments made to match the simplified early branching. dgisselq 3011d 06h /zipcpu/trunk/doc/
85 Minor update/correction to operand B definition. dgisselq 3037d 04h /zipcpu/trunk/doc/
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 3041d 08h /zipcpu/trunk/doc/
78 Found/corrected annoying bug in floating point documentation of the opcode
table.		 dgisselq 3041d 08h /zipcpu/trunk/doc/
73 Documentations updates. dgisselq 3042d 07h /zipcpu/trunk/doc/
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.		 dgisselq 3042d 07h /zipcpu/trunk/doc/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3048d 12h /zipcpu/trunk/doc/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 3083d 12h /zipcpu/trunk/doc/
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 3083d 12h /zipcpu/trunk/doc/
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.		 dgisselq 3129d 06h /zipcpu/trunk/doc/
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 3129d 06h /zipcpu/trunk/doc/
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.		 dgisselq 3132d 09h /zipcpu/trunk/doc/
37 Fixed some minor spelling errors. dgisselq 3141d 02h /zipcpu/trunk/doc/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3141d 15h /zipcpu/trunk/doc/
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.		 dgisselq 3158d 05h /zipcpu/trunk/doc/
33 Finally finished a first draft of the full specification! dgisselq 3170d 08h /zipcpu/trunk/doc/

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