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[/] [zipcpu/] [trunk/] [doc/] - Rev 162

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162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2882d 15h /zipcpu/trunk/doc
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 2882d 15h /zipcpu/trunk/doc
153 Adds internal link functionality to the specification document format. dgisselq 2898d 03h /zipcpu/trunk/doc
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.		 dgisselq 2937d 12h /zipcpu/trunk/doc
107 Adding a missing file. dgisselq 2990d 04h /zipcpu/trunk/doc
106 Updated to allow building without the sources for the graphics used in the
document.		 dgisselq 2990d 08h /zipcpu/trunk/doc
92 Adjustments made to match the simplified early branching. dgisselq 3036d 05h /zipcpu/trunk/doc
85 Minor update/correction to operand B definition. dgisselq 3062d 03h /zipcpu/trunk/doc
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 3066d 07h /zipcpu/trunk/doc
78 Found/corrected annoying bug in floating point documentation of the opcode
table.		 dgisselq 3066d 07h /zipcpu/trunk/doc
73 Documentations updates. dgisselq 3067d 07h /zipcpu/trunk/doc
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.		 dgisselq 3067d 07h /zipcpu/trunk/doc
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3073d 11h /zipcpu/trunk/doc
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 3108d 11h /zipcpu/trunk/doc
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 3108d 12h /zipcpu/trunk/doc
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.		 dgisselq 3154d 05h /zipcpu/trunk/doc
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 3154d 05h /zipcpu/trunk/doc
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.		 dgisselq 3157d 08h /zipcpu/trunk/doc
37 Fixed some minor spelling errors. dgisselq 3166d 01h /zipcpu/trunk/doc
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3166d 14h /zipcpu/trunk/doc

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