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Rev Log message Author Age Path
189 Final, as delivered, ORCONF slides. dgisselq 2078d 00h /zipcpu/trunk/doc/
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2110d 03h /zipcpu/trunk/doc/
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.
dgisselq 2122d 03h /zipcpu/trunk/doc/
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2158d 03h /zipcpu/trunk/doc/
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.
dgisselq 2171d 03h /zipcpu/trunk/doc/
164 Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU.
dgisselq 2179d 08h /zipcpu/trunk/doc/
163 Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set!
dgisselq 2187d 10h /zipcpu/trunk/doc/
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2187d 11h /zipcpu/trunk/doc/
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 2187d 11h /zipcpu/trunk/doc/
153 Adds internal link functionality to the specification document format. dgisselq 2202d 23h /zipcpu/trunk/doc/
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.
dgisselq 2242d 08h /zipcpu/trunk/doc/
107 Adding a missing file. dgisselq 2295d 00h /zipcpu/trunk/doc/
106 Updated to allow building without the sources for the graphics used in the
document.
dgisselq 2295d 04h /zipcpu/trunk/doc/
92 Adjustments made to match the simplified early branching. dgisselq 2341d 01h /zipcpu/trunk/doc/
85 Minor update/correction to operand B definition. dgisselq 2366d 23h /zipcpu/trunk/doc/
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 2371d 03h /zipcpu/trunk/doc/
78 Found/corrected annoying bug in floating point documentation of the opcode
table.
dgisselq 2371d 03h /zipcpu/trunk/doc/
73 Documentations updates. dgisselq 2372d 02h /zipcpu/trunk/doc/
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.
dgisselq 2372d 02h /zipcpu/trunk/doc/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2378d 07h /zipcpu/trunk/doc/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 2413d 07h /zipcpu/trunk/doc/
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 2413d 07h /zipcpu/trunk/doc/
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.
dgisselq 2459d 01h /zipcpu/trunk/doc/
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 2459d 01h /zipcpu/trunk/doc/
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 2462d 04h /zipcpu/trunk/doc/
37 Fixed some minor spelling errors. dgisselq 2470d 21h /zipcpu/trunk/doc/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2471d 10h /zipcpu/trunk/doc/
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.
dgisselq 2488d 00h /zipcpu/trunk/doc/
33 Finally finished a first draft of the full specification! dgisselq 2500d 03h /zipcpu/trunk/doc/
32 Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.

The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create.
dgisselq 2500d 11h /zipcpu/trunk/doc/

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