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[/] [zipcpu/] [trunk/] [doc/] - Rev 196

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69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3055d 05h /zipcpu/trunk/doc/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 3090d 06h /zipcpu/trunk/doc/
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 3090d 06h /zipcpu/trunk/doc/
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.		 dgisselq 3136d 00h /zipcpu/trunk/doc/
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 3136d 00h /zipcpu/trunk/doc/
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.		 dgisselq 3139d 03h /zipcpu/trunk/doc/
37 Fixed some minor spelling errors. dgisselq 3147d 20h /zipcpu/trunk/doc/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3148d 08h /zipcpu/trunk/doc/
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.		 dgisselq 3164d 23h /zipcpu/trunk/doc/
33 Finally finished a first draft of the full specification! dgisselq 3177d 01h /zipcpu/trunk/doc/

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