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[/] [zipcpu/] [trunk/] [doc/] - Rev 70

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Rev	Log message	Author	Age	Path
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3069d 04h	/zipcpu/trunk/doc/
68	Updated specification, includes well illustrated pipeline discussion.	dgisselq	3104d 05h	/zipcpu/trunk/doc/
67	Includes timing diagrams in support of a very descriptive specification section.	dgisselq	3104d 05h	/zipcpu/trunk/doc/
49	Final set of changes finishing the Dhrystone package. Dhrystone, as implemented by hand in assembly, now works.	dgisselq	3149d 23h	/zipcpu/trunk/doc/
47	Added some new graphics, includes the file for the Zip Bones system.	dgisselq	3149d 23h	/zipcpu/trunk/doc/
39	Here's the documentation update to support the pipelined read/writes of the bus from the CPU, as well as the test file that proved they worked.	dgisselq	3153d 02h	/zipcpu/trunk/doc/
37	Fixed some minor spelling errors.	dgisselq	3161d 19h	/zipcpu/trunk/doc/
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3162d 07h	/zipcpu/trunk/doc/
35	I updated the system diagram to reflect the new version that has a direct memory access controller, rather than the (useless) manual cache.	dgisselq	3178d 22h	/zipcpu/trunk/doc/
33	Finally finished a first draft of the full specification!	dgisselq	3191d 00h	/zipcpu/trunk/doc/
32	Updated the document to match the most recent changes to the CPU. Specifically, these include the re-instatement of the full SUB command with immediate offset, and ... others I cannot remember. The new document also describes what conditions create pipeline stalls, together with how many cycles each stall condition will create.	dgisselq	3191d 08h	/zipcpu/trunk/doc/
24	Lots more changes to the spec. It's still not done, but it is more complete than before.	dgisselq	3194d 09h	/zipcpu/trunk/doc/
23	Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec. These were quickly removed.	dgisselq	3196d 05h	/zipcpu/trunk/doc/
22		dgisselq	3196d 05h	/zipcpu/trunk/doc/
21	This update adds an incomplete version of the specification for the chip. I ned to come back to this and do a lot more writing, but it is a start.	dgisselq	3196d 05h	/zipcpu/trunk/doc/
10	Here's the watchdog timer code, as well as some pictures of the register set.	dgisselq	3216d 22h	/zipcpu/trunk/doc/
8	Fixed the rotate left instruction to work in the zasm parser, and to be properly referenced in the simulator. The instruction set documentation was also adjusted to reflect what the CPU actually does.	dgisselq	3217d 05h	/zipcpu/trunk/doc/
7	Here's the iset.html file that was at one time in the gfx directory, but which could not be moved due to a bad gateway error ... (Grrr).	dgisselq	3217d 06h	/zipcpu/trunk/doc/
6	Trying to move iset.html from gfx directory.	dgisselq	3217d 06h	/zipcpu/trunk/doc/
5	Updated colors in the graphics.	dgisselq	3217d 06h	/zipcpu/trunk/doc/

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[/] [zipcpu/] [trunk/] [doc/] - Rev 70

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