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[/] [zipcpu/] [trunk/] [doc/] [src/] - Rev 199

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Rev Log message Author Age Path
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.
dgisselq 2020d 07h /zipcpu/trunk/doc/src/
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.
dgisselq 2131d 10h /zipcpu/trunk/doc/src/
153 Adds internal link functionality to the specification document format. dgisselq 2163d 06h /zipcpu/trunk/doc/src/
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.
dgisselq 2202d 15h /zipcpu/trunk/doc/src/
92 Adjustments made to match the simplified early branching. dgisselq 2301d 08h /zipcpu/trunk/doc/src/
73 Documentations updates. dgisselq 2332d 10h /zipcpu/trunk/doc/src/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2338d 14h /zipcpu/trunk/doc/src/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 2373d 15h /zipcpu/trunk/doc/src/
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 2422d 12h /zipcpu/trunk/doc/src/
37 Fixed some minor spelling errors. dgisselq 2431d 04h /zipcpu/trunk/doc/src/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2431d 17h /zipcpu/trunk/doc/src/
33 Finally finished a first draft of the full specification! dgisselq 2460d 10h /zipcpu/trunk/doc/src/
32 Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.

The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create.
dgisselq 2460d 18h /zipcpu/trunk/doc/src/
24 Lots more changes to the spec. It's still not done, but it is more complete
than before.
dgisselq 2463d 19h /zipcpu/trunk/doc/src/
23 Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed.
dgisselq 2465d 15h /zipcpu/trunk/doc/src/
22 dgisselq 2465d 15h /zipcpu/trunk/doc/src/
21 This update adds an incomplete version of the specification for the chip.
I ned to come back to this and do a lot more writing, but it is a start.
dgisselq 2465d 15h /zipcpu/trunk/doc/src/

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