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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] - Rev 160

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Rev	Log message	Author	Age	Path
82	Found and (I hope) fixed a nasty bug that would send the prefetch into an endless loop whenever you jumped to an instruction at the last location in an unloaded cache line.	dgisselq	3036d 13h	/zipcpu/trunk/rtl/
81	Trying to clean up ISE generated warnings.	dgisselq	3036d 13h	/zipcpu/trunk/rtl/
80	Bug fix: declared the (combined) multiply to be signed again. Also changed the name of the generate'd for block, to keep ISE from complaining.	dgisselq	3036d 13h	/zipcpu/trunk/rtl/
71	This contains a bunch of bug fixes. (A lot ...) For example, the pipeline stall code has also seriously changed, to fixed the pipeline memory load/op stage conflict, while maintaining no-stall operation for operands that don't need an offset. This had a cascading effect, however, so that the multiply could no longer complete in a single cycle. Therefore, the timing on the multiplies was slowed down to two cycles from a single cycle. (It's the only two-cycle ALU operation ...) The illegal instruction code has also been fixed, so that illegal instructions no longer stalls the prefetch bus.	dgisselq	3041d 16h	/zipcpu/trunk/rtl/
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3047d 21h	/zipcpu/trunk/rtl/
66	Adjusted the support for the DEBUG_SCOPE within these so that it can be compiled in, or not, based upon an external build configuration file: cpudefs.v. That allows me to make that file project specific, while the rest of the CPU is shared among all projects.	dgisselq	3108d 21h	/zipcpu/trunk/rtl/
65	Lots of logic simplifications to the core, in addition to better support for illegal instruction detection and bus error detection. The biggest change had to deal with pushing the debug write interface into the ALU write processing path. This simplifies the logic of adjusting the PC and CC registers primarily, but also any writes to other registers. It also delays these register writes by a clock, but since the debug interface is already ridiculously slow I doubt that matters any.	dgisselq	3108d 21h	/zipcpu/trunk/rtl/
64	Shuffled some comments into here from elsewhere.	dgisselq	3108d 21h	/zipcpu/trunk/rtl/
63	Simplified bus interactions, and added support for detecting illegal instructions (i.e. bus errors) in the pipefetch routine.	dgisselq	3108d 21h	/zipcpu/trunk/rtl/
62	Simplified the subtraction logic, so the carry bit no longer depends on a separate 32-bit operation but becomes part of the subtract operation.	dgisselq	3108d 21h	/zipcpu/trunk/rtl/

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