OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] - Rev 204

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 2915d 14h /zipcpu/trunk/rtl/
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.		 dgisselq 2918d 12h /zipcpu/trunk/rtl/
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.		 dgisselq 2933d 02h /zipcpu/trunk/rtl/
132 Lots of minor bug fixes. dgisselq 2933d 02h /zipcpu/trunk/rtl/
131 Fixed a variable use before declaration error. dgisselq 2933d 03h /zipcpu/trunk/rtl/
130 Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction.		 dgisselq 2933d 03h /zipcpu/trunk/rtl/
129 Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed.		 dgisselq 2933d 03h /zipcpu/trunk/rtl/
128 Cleaned up some comments. dgisselq 2933d 03h /zipcpu/trunk/rtl/
118 Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler.		 dgisselq 2952d 03h /zipcpu/trunk/rtl/
115 A bug fix, applies to when there are more than 9 interrupt lines into the CPU. dgisselq 2952d 11h /zipcpu/trunk/rtl/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.