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[/] [zipcpu/] [trunk/] [rtl/] [Makefile] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 987d 02h /zipcpu/trunk/rtl/Makefile
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1726d 11h /zipcpu/trunk/rtl/Makefile
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 1852d 11h /zipcpu/trunk/rtl/Makefile
157 Added the divide unit to the list of ZipCPU dependencies. dgisselq 1994d 05h /zipcpu/trunk/rtl/Makefile
105 Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC.
dgisselq 2091d 14h /zipcpu/trunk/rtl/Makefile
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2169d 13h /zipcpu/trunk/rtl/Makefile
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.
dgisselq 2240d 16h /zipcpu/trunk/rtl/Makefile
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.
dgisselq 2253d 13h /zipcpu/trunk/rtl/Makefile
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2262d 16h /zipcpu/trunk/rtl/Makefile
18 A couple of changes: Registers can now be changed via the debug interface.
Also, in anticipation of being able to interrupt the break the processor,
the CPU now exports an interrupt line to the external environment to tell
when it has been halted. Thus, if it gets halted by a break instruction,
the ZipSystem will interrupt whatever's in its environment so that the
debugger can come and examine its state.

Oh, and one other: because you can't examine the state of the CPU without
halting it, I modified the debug control register to export the four
useful flags: break-enable, interrupts enabled, and sleep (step comes for
free in this implementation).
dgisselq 2298d 04h /zipcpu/trunk/rtl/Makefile
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2318d 08h /zipcpu/trunk/rtl/Makefile

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