OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Rev 15

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
15 Updated the core CPUOPS module to make certain that the carry was properly
set on right shifts. (Carry is then the last bit shifted out to the right,
and has no relation to the high order bits of the word.) Also fixed a bug
in the busdelay.v file that prevented our Quad SPI flash controller from
working. (This bug fix has not yet been tested ...) Our test.S program, the
closest thing we have to a regression test and found in the sw/zasm directory,
still successfully passes in Verilator.
dgisselq 2601d 11h /zipcpu/trunk/rtl/aux/busdelay.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2618d 01h /zipcpu/trunk/rtl/aux/busdelay.v

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.