| Rev |
Log message |
Author |
Age |
Path |
| 175 |
Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register. |
dgisselq |
2779d 23h |
/zipcpu/trunk/rtl/core/ |
| 174 |
Simplified the divide to improve timing performance. |
dgisselq |
2779d 23h |
/zipcpu/trunk/rtl/core/ |
| 160 |
Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.) |
dgisselq |
2872d 19h |
/zipcpu/trunk/rtl/core/ |
| 145 |
This fixes the pipelined memory problem that was introduced a while back to
fix ... pipelined memory conflicts. This appears to maintain the success
of the fix, while recovering the pipeline memory performance that was had
before. |
dgisselq |
2905d 18h |
/zipcpu/trunk/rtl/core/ |
| 140 |
Minor changes, but fixes build of zippy_tb.cpp. |
dgisselq |
2909d 07h |
/zipcpu/trunk/rtl/core/ |
| 138 |
This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed. |
dgisselq |
2912d 05h |
/zipcpu/trunk/rtl/core/ |
| 133 |
Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies. |
dgisselq |
2926d 19h |
/zipcpu/trunk/rtl/core/ |
| 132 |
Lots of minor bug fixes. |
dgisselq |
2926d 19h |
/zipcpu/trunk/rtl/core/ |
| 131 |
Fixed a variable use before declaration error. |
dgisselq |
2926d 19h |
/zipcpu/trunk/rtl/core/ |
| 130 |
Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction. |
dgisselq |
2926d 19h |
/zipcpu/trunk/rtl/core/ |
| 129 |
Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed. |
dgisselq |
2926d 19h |
/zipcpu/trunk/rtl/core/ |
| 118 |
Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler. |
dgisselq |
2945d 20h |
/zipcpu/trunk/rtl/core/ |
| 105 |
Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC. |
dgisselq |
2970d 04h |
/zipcpu/trunk/rtl/core/ |
| 91 |
Minor updates. |
dgisselq |
3010d 21h |
/zipcpu/trunk/rtl/core/ |
| 90 |
Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two. |
dgisselq |
3010d 21h |
/zipcpu/trunk/rtl/core/ |
| 88 |
Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ... |
dgisselq |
3034d 21h |
/zipcpu/trunk/rtl/core/ |
| 83 |
Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)
Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)
Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true. |
dgisselq |
3036d 20h |
/zipcpu/trunk/rtl/core/ |
| 82 |
Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line. |
dgisselq |
3036d 20h |
/zipcpu/trunk/rtl/core/ |
| 81 |
Trying to clean up ISE generated warnings. |
dgisselq |
3036d 20h |
/zipcpu/trunk/rtl/core/ |
| 80 |
Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining. |
dgisselq |
3036d 20h |
/zipcpu/trunk/rtl/core/ |
| 71 |
This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus. |
dgisselq |
3041d 23h |
/zipcpu/trunk/rtl/core/ |
| 69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3048d 03h |
/zipcpu/trunk/rtl/core/ |
| 65 |
Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any. |
dgisselq |
3109d 03h |
/zipcpu/trunk/rtl/core/ |
| 63 |
Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine. |
dgisselq |
3109d 04h |
/zipcpu/trunk/rtl/core/ |
| 62 |
Simplified the subtraction logic, so the carry bit no longer depends on
a separate 32-bit operation but becomes part of the subtract operation. |
dgisselq |
3109d 04h |
/zipcpu/trunk/rtl/core/ |
| 56 |
Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.
A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used. |
dgisselq |
3119d 06h |
/zipcpu/trunk/rtl/core/ |
| 49 |
Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works. |
dgisselq |
3128d 22h |
/zipcpu/trunk/rtl/core/ |
| 48 |
Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction. |
dgisselq |
3128d 22h |
/zipcpu/trunk/rtl/core/ |
| 38 |
A couple of quick updates:
- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.
Documentation changes coming shortly. |
dgisselq |
3132d 03h |
/zipcpu/trunk/rtl/core/ |
| 36 |
*Lots* of changes to increase processing speed and remove pipeline stalls.
Removed the useless flash cache, replacing it with a proper DMA controller.
"make test" in the main directory now runs a test program in Verilator and
reports on the results. |
dgisselq |
3141d 06h |
/zipcpu/trunk/rtl/core/ |
