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[/] [zipcpu/] [trunk/] [rtl/] [core/] [div.v] - Rev 209

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Rev Log message Author Age Path
209 8b bytes, + formal verification throughout + dcache dgisselq 989d 01h /zipcpu/trunk/rtl/core/div.v
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 1709d 12h /zipcpu/trunk/rtl/core/div.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1728d 10h /zipcpu/trunk/rtl/core/div.v
196 Updated internal documentation. dgisselq 1854d 10h /zipcpu/trunk/rtl/core/div.v
174 Simplified the divide to improve timing performance. dgisselq 1903d 08h /zipcpu/trunk/rtl/core/div.v
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 1996d 03h /zipcpu/trunk/rtl/core/div.v
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...
dgisselq 2158d 05h /zipcpu/trunk/rtl/core/div.v
81 Trying to clean up ISE generated warnings. dgisselq 2160d 04h /zipcpu/trunk/rtl/core/div.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2171d 12h /zipcpu/trunk/rtl/core/div.v

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