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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 1350d 15h /zipcpu/trunk/rtl/core/memops.v
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 2071d 03h /zipcpu/trunk/rtl/core/memops.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 2090d 01h /zipcpu/trunk/rtl/core/memops.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2533d 03h /zipcpu/trunk/rtl/core/memops.v
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.
dgisselq 2613d 21h /zipcpu/trunk/rtl/core/memops.v
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2626d 06h /zipcpu/trunk/rtl/core/memops.v
3 Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.

Other tweaks were made to try to reduce code complexity.
dgisselq 2681d 04h /zipcpu/trunk/rtl/core/memops.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2681d 21h /zipcpu/trunk/rtl/core/memops.v

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