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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pfcache.v] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 1857d 08h /zipcpu/trunk/rtl/core/pfcache.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 2596d 18h /zipcpu/trunk/rtl/core/pfcache.v
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2722d 17h /zipcpu/trunk/rtl/core/pfcache.v
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed.		 dgisselq 2771d 16h /zipcpu/trunk/rtl/core/pfcache.v
129 Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed.		 dgisselq 2918d 12h /zipcpu/trunk/rtl/core/pfcache.v
118 Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler.		 dgisselq 2937d 12h /zipcpu/trunk/rtl/core/pfcache.v
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...		 dgisselq 3026d 13h /zipcpu/trunk/rtl/core/pfcache.v
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.		 dgisselq 3028d 12h /zipcpu/trunk/rtl/core/pfcache.v
71 This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus.		 dgisselq 3033d 15h /zipcpu/trunk/rtl/core/pfcache.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3039d 20h /zipcpu/trunk/rtl/core/pfcache.v

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