Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipemem.v] - Rev 65


Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine.
dgisselq 2484d 17h /zipcpu/trunk/rtl/core/pipemem.v
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.
dgisselq 2494d 19h /zipcpu/trunk/rtl/core/pipemem.v
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.
dgisselq 2504d 11h /zipcpu/trunk/rtl/core/pipemem.v

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.