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[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Rev 205

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205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 1767d 09h /zipcpu/trunk/rtl/core/prefetch.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1786d 06h /zipcpu/trunk/rtl/core/prefetch.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2229d 08h /zipcpu/trunk/rtl/core/prefetch.v
63 Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine.
dgisselq 2290d 08h /zipcpu/trunk/rtl/core/prefetch.v
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.
dgisselq 2310d 02h /zipcpu/trunk/rtl/core/prefetch.v
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2322d 11h /zipcpu/trunk/rtl/core/prefetch.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2378d 02h /zipcpu/trunk/rtl/core/prefetch.v

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