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[/] [zipcpu/] [trunk/] [rtl/] [core] - Rev 196

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Rev	Log message	Author	Age	Path
91	Minor updates.	dgisselq	3010d 22h	/zipcpu/trunk/rtl/core
90	Removed MOV x(PC),PC from the list of possible early branching instructions. ADD X,PC and LDI X,PC are now the only recognized early branching instructions. This was done to spare logic, although I don't think I spared more than a LUT or two.	dgisselq	3010d 22h	/zipcpu/trunk/rtl/core
88	Eliminated some warnings. The div fixes were to simplify the logic, even though the result is less readable ...	dgisselq	3034d 22h	/zipcpu/trunk/rtl/core
83	Added a flag to indicate whether an exception took place on the first or second half of a VLIW instruction--will be zero in non-VLIW mode, equivalent to the second half of the instruction having caused the exception. (Expect these flags to be reordered some time in the future into a less haphazard ordering ...) Vastly simplified the pipeline logic, primarily for op_stall, but also touched opA and opB. (Trying to fit within timing on Spartan 6 ...) Changed division instruction to include a reset on clear_pipeline, to make certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is true.	dgisselq	3036d 20h	/zipcpu/trunk/rtl/core
82	Found and (I hope) fixed a nasty bug that would send the prefetch into an endless loop whenever you jumped to an instruction at the last location in an unloaded cache line.	dgisselq	3036d 21h	/zipcpu/trunk/rtl/core
81	Trying to clean up ISE generated warnings.	dgisselq	3036d 21h	/zipcpu/trunk/rtl/core
80	Bug fix: declared the (combined) multiply to be signed again. Also changed the name of the generate'd for block, to keep ISE from complaining.	dgisselq	3036d 21h	/zipcpu/trunk/rtl/core
71	This contains a bunch of bug fixes. (A lot ...) For example, the pipeline stall code has also seriously changed, to fixed the pipeline memory load/op stage conflict, while maintaining no-stall operation for operands that don't need an offset. This had a cascading effect, however, so that the multiply could no longer complete in a single cycle. Therefore, the timing on the multiplies was slowed down to two cycles from a single cycle. (It's the only two-cycle ALU operation ...) The illegal instruction code has also been fixed, so that illegal instructions no longer stalls the prefetch bus.	dgisselq	3042d 00h	/zipcpu/trunk/rtl/core
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3048d 04h	/zipcpu/trunk/rtl/core
65	Lots of logic simplifications to the core, in addition to better support for illegal instruction detection and bus error detection. The biggest change had to deal with pushing the debug write interface into the ALU write processing path. This simplifies the logic of adjusting the PC and CC registers primarily, but also any writes to other registers. It also delays these register writes by a clock, but since the debug interface is already ridiculously slow I doubt that matters any.	dgisselq	3109d 04h	/zipcpu/trunk/rtl/core

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