URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Rev 180

Rev	Log message	Author	Age	Path
160	Logic updates, and bug fix corrections to bring this in line with the current XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved, this update pushes those improvements to the mainline.)	dgisselq	2894d 20h	/zipcpu/trunk/rtl/peripherals/wbdmac.v
88	Eliminated some warnings. The div fixes were to simplify the logic, even though the result is less readable ...	dgisselq	3056d 22h	/zipcpu/trunk/rtl/peripherals/wbdmac.v
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3070d 04h	/zipcpu/trunk/rtl/peripherals/wbdmac.v
48	Files added/updated to get Dhrystone benchmark to work. Several fixes to the CPU in the process, 'cause it wasn't working. Stall-less ALU ops now work better, to include grabbing the memory result as it comes out of the memory unit and placing it straight into either ALU or memory unit for the next instruction.	dgisselq	3150d 22h	/zipcpu/trunk/rtl/peripherals/wbdmac.v
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3163d 07h	/zipcpu/trunk/rtl/peripherals/wbdmac.v