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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipcounter.v] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 993d 03h /zipcpu/trunk/rtl/peripherals/zipcounter.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1732d 12h /zipcpu/trunk/rtl/peripherals/zipcounter.v
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 1907d 10h /zipcpu/trunk/rtl/peripherals/zipcounter.v
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2000d 06h /zipcpu/trunk/rtl/peripherals/zipcounter.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2175d 14h /zipcpu/trunk/rtl/peripherals/zipcounter.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2324d 09h /zipcpu/trunk/rtl/peripherals/zipcounter.v

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