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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipjiffies.v] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 1887d 09h /zipcpu/trunk/rtl/peripherals/zipjiffies.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 2626d 19h /zipcpu/trunk/rtl/peripherals/zipjiffies.v
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2894d 12h /zipcpu/trunk/rtl/peripherals/zipjiffies.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 3069d 21h /zipcpu/trunk/rtl/peripherals/zipjiffies.v
9 This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.

Lots of work to get it working.

Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself.
dgisselq 3217d 14h /zipcpu/trunk/rtl/peripherals/zipjiffies.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 3218d 15h /zipcpu/trunk/rtl/peripherals/zipjiffies.v

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