| Rev |
Log message |
Author |
Age |
Path |
| 180 |
Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not. |
dgisselq |
3103d 20h |
/zipcpu/trunk/rtl |
| 179 |
Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary. |
dgisselq |
3103d 20h |
/zipcpu/trunk/rtl |
| 178 |
Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs. |
dgisselq |
3103d 20h |
/zipcpu/trunk/rtl |
| 177 |
Fixed the illegal address logic to be more precise. |
dgisselq |
3103d 20h |
/zipcpu/trunk/rtl |
| 176 |
Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed. |
dgisselq |
3103d 20h |
/zipcpu/trunk/rtl |
| 175 |
Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register. |
dgisselq |
3103d 20h |
/zipcpu/trunk/rtl |
| 174 |
Simplified the divide to improve timing performance. |
dgisselq |
3103d 20h |
/zipcpu/trunk/rtl |
| 160 |
Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.) |
dgisselq |
3196d 16h |
/zipcpu/trunk/rtl |
| 157 |
Added the divide unit to the list of ZipCPU dependencies. |
dgisselq |
3196d 16h |
/zipcpu/trunk/rtl |
| 145 |
This fixes the pipelined memory problem that was introduced a while back to
fix ... pipelined memory conflicts. This appears to maintain the success
of the fix, while recovering the pipeline memory performance that was had
before. |
dgisselq |
3229d 14h |
/zipcpu/trunk/rtl |
| 144 |
Makes the auto-reload capability a configuration option, and fills out the
reset so that it is properly implemented. |
dgisselq |
3229d 15h |
/zipcpu/trunk/rtl |
| 140 |
Minor changes, but fixes build of zippy_tb.cpp. |
dgisselq |
3233d 04h |
/zipcpu/trunk/rtl |
| 138 |
This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed. |
dgisselq |
3236d 01h |
/zipcpu/trunk/rtl |
| 133 |
Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies. |
dgisselq |
3250d 16h |
/zipcpu/trunk/rtl |
| 132 |
Lots of minor bug fixes. |
dgisselq |
3250d 16h |
/zipcpu/trunk/rtl |
| 131 |
Fixed a variable use before declaration error. |
dgisselq |
3250d 16h |
/zipcpu/trunk/rtl |
| 130 |
Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction. |
dgisselq |
3250d 16h |
/zipcpu/trunk/rtl |
| 129 |
Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed. |
dgisselq |
3250d 16h |
/zipcpu/trunk/rtl |
| 128 |
Cleaned up some comments. |
dgisselq |
3250d 16h |
/zipcpu/trunk/rtl |
| 118 |
Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler. |
dgisselq |
3269d 17h |
/zipcpu/trunk/rtl |
