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[/] [zipcpu/] [trunk/] [rtl] - Rev 201

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140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 2909d 08h /zipcpu/trunk/rtl
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.		 dgisselq 2912d 05h /zipcpu/trunk/rtl
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.		 dgisselq 2926d 20h /zipcpu/trunk/rtl
132 Lots of minor bug fixes. dgisselq 2926d 20h /zipcpu/trunk/rtl
131 Fixed a variable use before declaration error. dgisselq 2926d 20h /zipcpu/trunk/rtl
130 Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction.		 dgisselq 2926d 20h /zipcpu/trunk/rtl
129 Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed.		 dgisselq 2926d 20h /zipcpu/trunk/rtl
128 Cleaned up some comments. dgisselq 2926d 20h /zipcpu/trunk/rtl
118 Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler.		 dgisselq 2945d 20h /zipcpu/trunk/rtl
115 A bug fix, applies to when there are more than 9 interrupt lines into the CPU. dgisselq 2946d 04h /zipcpu/trunk/rtl

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