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[/] [zipcpu/] [trunk/] [sw/] - Rev 121

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Rev Log message Author Age Path
96 Added the longjump functionality, so that the assembler will properly assemble
instructions to arbitrary 32-bit addresses.		 dgisselq 2975d 04h /zipcpu/trunk/sw/
95 Fixed a bug whereby a mistaken code for CLR was masking a valid LDI of a large
integer value.		 dgisselq 2977d 10h /zipcpu/trunk/sw/
94 These changes make it possible to build binutils-2.25/ here in this
directory. "make binutils" should be all that is necessary to build the
entire binutils package for the Zip CPU.

The default configure script, run from gas-script.sh below, will build and
install these utilities in an install/ subdirectory made below sw/.		 dgisselq 3002d 07h /zipcpu/trunk/sw/
93 A BINUTILS BACKEND IS NOW AVAILABLE!!!! dgisselq 3010d 05h /zipcpu/trunk/sw/
89 Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions.

Further zopcodes.cpp contains several bug fixes.		 dgisselq 3010d 05h /zipcpu/trunk/sw/
70 Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes.		 dgisselq 3041d 07h /zipcpu/trunk/sw/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3047d 11h /zipcpu/trunk/sw/
60 Fixed assembler processing of jump instructions, so that the new fast
return instruction can be used. The test file was modified to test
pipelined value passing within the CPU. That's where the value gets
(re)used before being stored back in the register file. As of this release,
all tests work.		 dgisselq 3108d 11h /zipcpu/trunk/sw/
59 Adjusted these library routines to use the new stack frame and calling
conventions.		 dgisselq 3108d 11h /zipcpu/trunk/sw/
55 A test was added to double check whether carry following right shifts worked.
This was a necessary part of getting two cycle linear feedback shift register
operations working for a memory test on a XuLA2 board. With this, I can now
verify that such feedback registers work for pseudorandom number purposes.		 dgisselq 3118d 14h /zipcpu/trunk/sw/

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