OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk] - Rev 195

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
195 Adds a new mode that can handle a delayed stall signal. dgisselq 2809d 16h /zipcpu/trunk
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2809d 16h /zipcpu/trunk
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 2809d 16h /zipcpu/trunk
192 Fixed a bug with constant alignment in the assembler. dgisselq 2809d 16h /zipcpu/trunk
191 Updated toolchain, more information on the example debugger. dgisselq 2824d 19h /zipcpu/trunk
190 Added the copyright statement back in. dgisselq 2826d 11h /zipcpu/trunk
189 Final, as delivered, ORCONF slides. dgisselq 2826d 11h /zipcpu/trunk
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger.
dgisselq 2858d 13h /zipcpu/trunk
187 Updated to match changed register definitions within the core. dgisselq 2858d 14h /zipcpu/trunk
186 Now allows profile dumping for ELF executables. dgisselq 2858d 14h /zipcpu/trunk
185 Now includes the proper flags for building with ELF executable file support. dgisselq 2858d 14h /zipcpu/trunk
184 Adjusted the illegal instruction option documentation. dgisselq 2858d 14h /zipcpu/trunk
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2858d 14h /zipcpu/trunk
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.
dgisselq 2858d 14h /zipcpu/trunk
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2858d 14h /zipcpu/trunk
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2858d 14h /zipcpu/trunk
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2858d 14h /zipcpu/trunk
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs.
dgisselq 2858d 14h /zipcpu/trunk
177 Fixed the illegal address logic to be more precise. dgisselq 2858d 14h /zipcpu/trunk
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed.
dgisselq 2858d 14h /zipcpu/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.