OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu] - Rev 141

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
141 Fixes two bugs: one causing merged strings in the read only string section to
be referenced at the wrong address, and the second which caused the assembler
to fail at SYMBOL-OFFSET references.
dgisselq 2452d 23h /zipcpu
140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 2455d 11h /zipcpu
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.
dgisselq 2458d 09h /zipcpu
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.
dgisselq 2458d 09h /zipcpu
137 This should (again) fix the bug of trying to build optest.cpp. dgisselq 2472d 02h /zipcpu
136 Oops --- missed a couple HOST_WIDE_INT values in a printf. This casts them
to (long), so that we can work on both PC's and ARMs.
dgisselq 2472d 03h /zipcpu
135 Replaced all occurrences of INTVAL(...) on printf lines with (long)INTVAL(...).
This should fix the problems zip-gcc was having while running on the ARM.
dgisselq 2472d 03h /zipcpu
134 Working updates, to keep this up to date with the RTL code. dgisselq 2472d 23h /zipcpu
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.
dgisselq 2472d 23h /zipcpu
132 Lots of minor bug fixes. dgisselq 2472d 23h /zipcpu
131 Fixed a variable use before declaration error. dgisselq 2473d 00h /zipcpu
130 Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction.
dgisselq 2473d 00h /zipcpu
129 Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed.
dgisselq 2473d 00h /zipcpu
128 Cleaned up some comments. dgisselq 2473d 00h /zipcpu
127 Lots of changes and bugfixes. The disassembler produces more readable output.
The assembler and linker will no longer automatically use LDIHI--in preparation
for switching to LONG_MPY. LDIHI/LDILO pairs have been changed to BREV/LDILO
pairs. Within the compiler, conditional moves have been rebuilt. They're not
perfect yet, but they are better. Lots of peephole optimizations, etc.
dgisselq 2473d 00h /zipcpu
126 Lots of changes preparing the assembly for an instruction set change. While
implemented, they are still commented out via #ifdef LONG_MPY. By defining
LONG_MPY, this new change set will take place.
dgisselq 2473d 00h /zipcpu
125 This patch contains minor updates. Two are important to mention: 1) It turns
the compare optimizations back on within the zip.md file, and 2) it fixes an
internal compiler fault that was causing the compiler to such up all of my
memory in an infinite recursion.
dgisselq 2481d 08h /zipcpu
124 Lots of changes, lots of bugfixes--both to the compiler as well as to the
assembler. (Ex: the assembler will now properly execute a LDI _sym+5,R0).
Many compiler optimizations have been turned off, however. They will probably
be turned back on in the near future--once I get this version proven without
them.
dgisselq 2482d 21h /zipcpu
123 This test now catches and tests some of the pipeline bugs I've been chasing. dgisselq 2482d 22h /zipcpu
122 This represents a major rewrite of the machine definition file, gcc/config/zip/
zip.md. In particular, the architecture has been changed from a "cc0"
architecture to one with a specific CC_REG and CCmode. Instructions in the
machine definition file must now explicitly set this register with their
results. The result is better condition code handling, better usage of the
conditional execution modes of certain instructions, and even some decent
optimizations.
dgisselq 2488d 02h /zipcpu

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.