URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu] - Rev 183

Rev	Log message	Author	Age	Path
163	Trimmed OR1K instruction set down from 219 instructions, to the minimum number of 48. Thanks to Olof for helping identify the minimal set!	dgisselq	2867d 10h	/zipcpu
162	Noted 64-bit integers are by extension, as are vector instructions.	dgisselq	2867d 11h	/zipcpu
161	Initial version of the ORConf slides, showing only the initial CPU survey.	dgisselq	2867d 11h	/zipcpu
160	Logic updates, and bug fix corrections to bring this in line with the current XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved, this update pushes those improvements to the mainline.)	dgisselq	2882d 23h	/zipcpu
159	Now supports building a simulator that can load ELF files, such as GCC and/or binutils will produce.	dgisselq	2882d 23h	/zipcpu
158	Now automatically builds the toolchain by default.	dgisselq	2882d 23h	/zipcpu
157	Added the divide unit to the list of ZipCPU dependencies.	dgisselq	2882d 23h	/zipcpu
156	Fixed a compiler warning for an unused result.	dgisselq	2882d 23h	/zipcpu
155	Improved debug trace quality, for finding bugs after the fact.	dgisselq	2882d 23h	/zipcpu
154	Added timing checks on the busy and valid signals: either one of the two is valid, or the whole is idle.	dgisselq	2882d 23h	/zipcpu