Subversion Repositories zipcpu

[/] [zipcpu] - Rev 209


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Rev Log message Author Age Path
209 8b bytes, + formal verification throughout + dcache dgisselq 1922d 18h /zipcpu
208 Add install and readme files, updated testb to capture initial variable status in Verilator dgisselq 2643d 06h /zipcpu
207 Updated the ELF support, and divide test-bench. dgisselq 2643d 06h /zipcpu
206 Updated assembler, fixes several bugs, adds better bug detection and reporting (fixes some segfaults on bugs) dgisselq 2643d 06h /zipcpu
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 2643d 06h /zipcpu
204 Added the two simulators back into the SVN repository dgisselq 2662d 01h /zipcpu
203 Removed the (now unused) old GCC compiler, v5.3.0 dgisselq 2662d 01h /zipcpu
202 Additional ZipCPU changes associated w 8b upgrade dgisselq 2662d 02h /zipcpu
201 RTL files for the 8-bit capable ZipCPU. dgisselq 2662d 03h /zipcpu
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.
dgisselq 2761d 10h /zipcpu
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.
dgisselq 2786d 23h /zipcpu
198 Added a copyright notice. dgisselq 2788d 03h /zipcpu
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 2788d 03h /zipcpu
196 Updated internal documentation. dgisselq 2788d 03h /zipcpu
195 Adds a new mode that can handle a delayed stall signal. dgisselq 2788d 03h /zipcpu
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2788d 03h /zipcpu
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 2788d 03h /zipcpu
192 Fixed a bug with constant alignment in the assembler. dgisselq 2788d 03h /zipcpu
191 Updated toolchain, more information on the example debugger. dgisselq 2803d 06h /zipcpu
190 Added the copyright statement back in. dgisselq 2804d 22h /zipcpu
189 Final, as delivered, ORCONF slides. dgisselq 2804d 22h /zipcpu
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
dgisselq 2837d 01h /zipcpu
187 Updated to match changed register definitions within the core. dgisselq 2837d 01h /zipcpu
186 Now allows profile dumping for ELF executables. dgisselq 2837d 01h /zipcpu
185 Now includes the proper flags for building with ELF executable file support. dgisselq 2837d 01h /zipcpu
184 Adjusted the illegal instruction option documentation. dgisselq 2837d 01h /zipcpu
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2837d 01h /zipcpu
182 Bug fix for fast memories. This now works for memories with single cycle
dgisselq 2837d 01h /zipcpu
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2837d 01h /zipcpu
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2837d 01h /zipcpu

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