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[/] [zipcpu] - Rev 209


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Rev Log message Author Age Path
189 Final, as delivered, ORCONF slides. dgisselq 2801d 02h /zipcpu
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
dgisselq 2833d 04h /zipcpu
187 Updated to match changed register definitions within the core. dgisselq 2833d 05h /zipcpu
186 Now allows profile dumping for ELF executables. dgisselq 2833d 05h /zipcpu
185 Now includes the proper flags for building with ELF executable file support. dgisselq 2833d 05h /zipcpu
184 Adjusted the illegal instruction option documentation. dgisselq 2833d 05h /zipcpu
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2833d 05h /zipcpu
182 Bug fix for fast memories. This now works for memories with single cycle
dgisselq 2833d 05h /zipcpu
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2833d 05h /zipcpu
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2833d 05h /zipcpu

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