| Rev |
Log message |
Author |
Age |
Path |
| 104 |
An updated build script, actually builds zip-gcc. |
dgisselq |
2977d 00h |
/ |
| 103 |
A barely functional, but somewhat working, version of GCC to check in.
If the Lord is willing, it should be accompanied by a newlib port soon.
That port should move the GCC status from barely functional but somewhat
working to functional and working, although not (yet) complete. |
dgisselq |
2977d 05h |
/ |
| 102 |
Updated bugfix version of the binutils patch, and a first patch of GCC.
The GCC patch is undergoing ongoing and active development. It is also known to
continue to contain active bugs. (It's not done yet.) |
dgisselq |
2979d 13h |
/ |
| 101 |
Adjusted the "BREAK" instruction so that it will now disassemble properly
with an operand. This was necessary to create a (trap_if ...) instruction
for the GCC compiler. |
dgisselq |
2981d 16h |
/ |
| 100 |
Some changes to support early branching: branches are now ADD #x,PC instructions
instead of MOV #x(PC),PC--providing greater range to the CPU. When that range
is insufficient, ZPARSER now recognizes long jump instructions coded as
LOD (PC),PC followed by the jump address. (This change was made necessary by
the need to build an assembler/linker that could create instructions that would
jump to any address in the 32-bit address space. In short, a part of the
ongoing GCC upgrade and rework.) |
dgisselq |
2981d 16h |
/ |
| 99 |
Added big-endian versus little-endian functionality. You can now specify which
your input file is as a command line parameter, and zdump will properly
disassemble the file. |
dgisselq |
2981d 16h |
/ |
| 98 |
Added justed longjump instructions from the previous (not used, broken)
functionality to the new LOD (PC),PC functionality. |
dgisselq |
2981d 16h |
/ |
| 97 |
Added longjump instructions. |
dgisselq |
2981d 16h |
/ |
| 96 |
Added the longjump functionality, so that the assembler will properly assemble
instructions to arbitrary 32-bit addresses. |
dgisselq |
2981d 16h |
/ |
| 95 |
Fixed a bug whereby a mistaken code for CLR was masking a valid LDI of a large
integer value. |
dgisselq |
2983d 22h |
/ |
| 94 |
These changes make it possible to build binutils-2.25/ here in this
directory. "make binutils" should be all that is necessary to build the
entire binutils package for the Zip CPU.
The default configure script, run from gas-script.sh below, will build and
install these utilities in an install/ subdirectory made below sw/. |
dgisselq |
3008d 19h |
/ |
| 93 |
A BINUTILS BACKEND IS NOW AVAILABLE!!!! |
dgisselq |
3016d 17h |
/ |
| 92 |
Adjustments made to match the simplified early branching. |
dgisselq |
3016d 17h |
/ |
| 91 |
Minor updates. |
dgisselq |
3016d 17h |
/ |
| 90 |
Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two. |
dgisselq |
3016d 17h |
/ |
| 89 |
Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions.
Further zopcodes.cpp contains several bug fixes. |
dgisselq |
3016d 17h |
/ |
| 88 |
Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ... |
dgisselq |
3040d 17h |
/ |
| 87 |
Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...) |
dgisselq |
3042d 15h |
/ |
| 86 |
Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W). |
dgisselq |
3042d 15h |
/ |
| 85 |
Minor update/correction to operand B definition. |
dgisselq |
3042d 15h |
/ |
| 84 |
Minor updates. |
dgisselq |
3042d 15h |
/ |
| 83 |
Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)
Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)
Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true. |
dgisselq |
3042d 15h |
/ |
| 82 |
Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line. |
dgisselq |
3042d 15h |
/ |
| 81 |
Trying to clean up ISE generated warnings. |
dgisselq |
3042d 15h |
/ |
| 80 |
Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining. |
dgisselq |
3042d 15h |
/ |
| 79 |
Adjusted the opcodes for NOOP, BREAK, and LOCK. |
dgisselq |
3046d 19h |
/ |
| 78 |
Found/corrected annoying bug in floating point documentation of the opcode
table. |
dgisselq |
3046d 19h |
/ |
| 77 |
First check-in: the test bench for the divide instruction. |
dgisselq |
3047d 18h |
/ |
| 76 |
The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions. |
dgisselq |
3047d 18h |
/ |
| 75 |
Modified for VLIW instructions. |
dgisselq |
3047d 18h |
/ |
