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Rev Log message Author Age Path
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2859d 00h /
172 Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg().
dgisselq 2859d 00h /
171 This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters.
dgisselq 2861d 06h /
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.
dgisselq 2871d 00h /
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2907d 00h /
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.
dgisselq 2920d 00h /
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.
dgisselq 2920d 00h /
166 Bugfix version. This fixes a problem whereby function addresses with offsets
were not properly calculated, together with properly setting up pcrelative
offsets when using the move function together with a label.
dgisselq 2920d 04h /
165 Added a test to make certain that the arithmetic right shift was properly
propagating the high order bit. (The test works under verilator, but didn't
initially work in Xilinx -- thus a difference between the two.)
dgisselq 2920d 04h /
164 Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU.
dgisselq 2928d 06h /
163 Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set!
dgisselq 2936d 08h /
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2936d 08h /
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 2936d 08h /
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2951d 20h /
159 Now supports building a simulator that can load ELF files, such as GCC and/or
binutils will produce.
dgisselq 2951d 20h /
158 Now automatically builds the toolchain by default. dgisselq 2951d 20h /
157 Added the divide unit to the list of ZipCPU dependencies. dgisselq 2951d 20h /
156 Fixed a compiler warning for an unused result. dgisselq 2951d 20h /
155 Improved debug trace quality, for finding bugs after the fact. dgisselq 2951d 20h /
154 Added timing checks on the busy and valid signals: either one of the two is
valid, or the whole is idle.
dgisselq 2951d 20h /

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