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Rev Log message Author Age Path
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.		 dgisselq 2789d 22h /
174 Simplified the divide to improve timing performance. dgisselq 2789d 22h /
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2789d 23h /
172 Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg().		 dgisselq 2789d 23h /
171 This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters.		 dgisselq 2792d 04h /
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.		 dgisselq 2801d 22h /
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2837d 22h /
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.		 dgisselq 2850d 22h /
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.		 dgisselq 2850d 22h /
166 Bugfix version. This fixes a problem whereby function addresses with offsets
were not properly calculated, together with properly setting up pcrelative
offsets when using the move function together with a label.		 dgisselq 2851d 02h /

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