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[/] - Rev 209

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Rev Log message Author Age Path
189 Final, as delivered, ORCONF slides. dgisselq 1869d 18h /
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger.
dgisselq 1901d 21h /
187 Updated to match changed register definitions within the core. dgisselq 1901d 21h /
186 Now allows profile dumping for ELF executables. dgisselq 1901d 21h /
185 Now includes the proper flags for building with ELF executable file support. dgisselq 1901d 21h /
184 Adjusted the illegal instruction option documentation. dgisselq 1901d 21h /
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 1901d 21h /
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.
dgisselq 1901d 21h /
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 1901d 21h /
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 1901d 21h /

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