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27 The big change to the test bench code in this directory is the support for
non-interactive operation. The test bench will now run in non-interactive
mode until either the CPU HALT's or executes a BUSY instruction. A 'HALT'
is deemed a test success, whereas a BUSY is deemed a test failure.

A usage() statement now informs the user what commands are available while
running the test bench interactively. (It looks a lot like the debugger looks
like, should you manage to get that up and running.)

The make file now also supports interactive and non-interactive testing via
the 'make itest' and 'make test' targets respectively.
dgisselq 2554d 18h /
26 Added signed and unsigned multiply opcodes to the assembler.

An opcode was added for a 'negate' instruction. This is a derived instruction
that turns into two instructions. Neg RX becomes an XOR -1,Rx followed by an
Add 1,Rx command. (Move 1+Rx,Rx would've stalled the bus by one cycle.)

Instructions now keep track of the source linenumber (but not yet filename)
where they were issued. That way, upon an error in linking at the end, the
instruction can be referenced by the proper line number. (Filenames are still
not implemented, hence include files may reference the line number of the
include file with no proper indication of that ... yet).

The OBJFILE intrface now supports a clos() function. This allows the
assembler to close and delete the object file for those cases where the
preprocessor encounters an error.

The master test file, sw/test.S, was adjuted as follows: many of the tests
within it can be separated by #ifdef lines. Hence, if you only wish to test
whether or not CARRY works, undefine all of the other ifdefs but leave the
CARRY_TEST defined. (PUSH_TEST, a test of the PUSH(RX,SP) macro, still doesn't
work because the assembler still doesn't implement macros. This is still a
coming feature.)

The master test file now has tests for the break function, as well as for the
new trap CC bit and the new multiply signed and unsigned instructions in the
ALU.

Many error conditions were added to the assembler preprocessor. Now, if an
EOF is encountered in anything but the INITIAL state (not within a macro),
an error will be created. Likewise, any unrecognized preprocessor directive
will create an error.

The lexical analyzer now supports character values, such as 'a' or '\n' using
a C-type syntax. (Tri-graphs are not supported.) It also supports such
extended syntax as '$GPG'. (Hmm ... wonder why I needed that?)

The lexical analyzer now recognizes and properly supports #line preprocessor
output statements. Theselines are then used to track what source line errors
occurr at.

Operand precedence has been adjusted, so the assembler should be able to
properly handle things like 5+3*8 and get the same number answer as 3*8+5.
(This has been implemented, although not thoroughly tested.)

Upon completion of any preprocessing file, the assembler now checks the status
of the preprocessor as returned by its exit code. Anything other than a zero
status will cause the assembler to delete the resulting object code file it is
building and exit with an error.

The assembler also supports the '-d' command line flag to turn on debugging in
the yacc processor (setting yydebug). It'll produce a lot of debugging output,
but it just might help to figure out what 'syntax error' is actually taking
place.
dgisselq 2554d 18h /
25 Lots of changes, hopefully all for the better. The result works in a
simulator, although it has yet to be tested yet in an FPGA--so it may still
have Xilinx build errors.

1. The wires brought from the CPU to the Zip System for the debug command
register were adjusted. They now include GIE and SLEEP, but no longer include
the step or break enable bits as these were fairly useless anyway.

2. The user and master A-Stall counters were re-labeled as instruction count
counters (which is what they are now anyway). This is for performance reasons
so that, after the fact, you can measure how many instructions per clock
you were actually able to achieve.

3. The CPU debug access port stall was adjusted so that the data port no longer
stalls when the CPU isn't halted. This can be useful, for example, when trying
to determine where th program counter is at without stalling the CPU. (You'll
still need to read two registers, the supervisor and user program counters, and
reading these registers still requires a write to the debug command port first,
so this still requires 4 single operand wishbone bus cycles.)

4. Signed and unsigned 16-bit multiply capabilities were added to the ALU
(cpuops.v) and support added in the Zip CPU master file as well.

5. The ZIP CPU now spports the TRAP bit in the CC register, so that after a user
interrupt the supervisor can tell that it was a user interrupt versus a hardware
interrupt. This bit is set any time the user disables the GIE bit, and cleared
any time the supervisor sets the GIE bit.

6. A reserved position was created in the CC register for a floating point
enable flag. This flag is permanently false, however, on the current
implementation as it doesn't implement floating point.

7. Logic was added to handle the break instruction. This instruction has now
been tested successfully in the simulator. If a break is issued, the CPU will
either halt (if in supervisor mode, or if in user mode with the break enable
bit set in the CC register), or the CPU will trip an interrupt for the
supervisor to transfer execution to a user-level debugging task.

8. After watching the CPU stall on a LDIHI followed by an LDILO, logic was
adjusted to keep the pipeline from stalling in thesee conditions. This lew
logic works for an 'A' operand, or equivalently for a 'B' operand with no
immediate. In the cases of such logic, the operand is loaded directly from the
output of the ALU into the input of the ALU skipping the operand read stage of
the pipelinle. This logic has not been tested on an FPGA yet, so it isn't clear
if it will break timing requirements or not. (Goal is 100 MHz clock.) As
of this new change, the CPU can now execute 0.48 instructions per clock, versus
the 0.44 it was getting before, across the test set.

9. Sleep logic was adjusted to prevent the user from switching to supervisor
mode and putting the processor to (infinite) sleep at the same time. The
justification was the fact that a user should not be able to halt the CPU when
other processes that might want it might still exist.

Other changes were made as well, but to other portions of the project. Those
will be checked in shortly.
dgisselq 2554d 19h /
24 Lots more changes to the spec. It's still not done, but it is more complete
than before.
dgisselq 2557d 08h /
23 Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed.
dgisselq 2559d 04h /
22 dgisselq 2559d 04h /
21 This update adds an incomplete version of the specification for the chip.
I ned to come back to this and do a lot more writing, but it is a start.
dgisselq 2559d 04h /
20 Added a quick README to the debugger directory. dgisselq 2560d 18h /
19 Here's the outlines of a debugger. dgisselq 2560d 18h /
18 A couple of changes: Registers can now be changed via the debug interface.
Also, in anticipation of being able to interrupt the break the processor,
the CPU now exports an interrupt line to the external environment to tell
when it has been halted. Thus, if it gets halted by a break instruction,
the ZipSystem will interrupt whatever's in its environment so that the
debugger can come and examine its state.

Oh, and one other: because you can't examine the state of the CPU without
halting it, I modified the debug control register to export the four
useful flags: break-enable, interrupts enabled, and sleep (step comes for
free in this implementation).
dgisselq 2560d 19h /
17 The ZOPCODES function zipi_to_string (ZIP CPU instruction to string, part of
the machine code dump) was adjusted to have closer to a fixed width output.
It no longer uses tab characters, which can have an unreliable effect.
dgisselq 2560d 19h /
16 The assembler now supports:
1. Multiple data elements on a line. These are lines like:
WORD 5,8,4,1
which place the words 5, 8, 4, and 1 directly into the object code to be
referenced as data. Prior to this release, these lines would assemble
properly but only place '5' as a data element into the object code.

2. The '-E' preprocessor only directive is now supported to produce output
from the preprocessor and see what is (or is not) happening there.

3. The preprocessor now validly places "#line" comments into the file, which
the assembler picks up and uses in it's error codes. These help identify
where errors took place.

4. Zasm now looks for the preprocessor (zpp) in the same directory zasm was
run from, using the same directory prefix as zasm, whenever zasm is given such
a directory prefix.

And ... perhaps other things I've forgotten about.
dgisselq 2562d 01h /
15 Updated the core CPUOPS module to make certain that the carry was properly
set on right shifts. (Carry is then the last bit shifted out to the right,
and has no relation to the high order bits of the word.) Also fixed a bug
in the busdelay.v file that prevented our Quad SPI flash controller from
working. (This bug fix has not yet been tested ...) Our test.S program, the
closest thing we have to a regression test and found in the sw/zasm directory,
still successfully passes in Verilator.
dgisselq 2564d 08h /
14 Removing zasm.cpp--the old assembler that never worked well. dgisselq 2564d 08h /
13 Finally! The beginnings of the new assembler. It's not really polished yet,
and it is quite clunky, but it works!! (Lots of bugs and features left to
fix/implement: #include, #define macro(), #line tracking through the
preprocessor, a means of finding include files (and the preprocessor!) and
more. But, as a beginning, the basics are functinoal.
dgisselq 2564d 08h /
12 Bunch of changes while trying to get a hello world program:
1. Right shifts by 32 or more now result in zero, or all of the top bit in the
case of ASRs.
2. zdump now properly includes addresses with dumped lines.
3. zparser now properly handles immediate values via the .DAT instruction.
dgisselq 2578d 23h /
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 2579d 08h /
10 Here's the watchdog timer code, as well as some pictures of the register
set.
dgisselq 2579d 21h /
9 This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.

Lots of work to get it working.

Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself.
dgisselq 2579d 21h /
8 Fixed the rotate left instruction to work in the zasm parser, and to be
properly referenced in the simulator. The instruction set documentation was
also adjusted to reflect what the CPU actually does.
dgisselq 2580d 04h /

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