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Rev Log message Author Age Path
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...
dgisselq 2464d 03h /
87 Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...)
dgisselq 2466d 01h /
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).
dgisselq 2466d 01h /
85 Minor update/correction to operand B definition. dgisselq 2466d 01h /
84 Minor updates. dgisselq 2466d 01h /
83 Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)

Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)

Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true.
dgisselq 2466d 01h /
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.
dgisselq 2466d 01h /
81 Trying to clean up ISE generated warnings. dgisselq 2466d 01h /
80 Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining.
dgisselq 2466d 01h /
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 2470d 05h /
78 Found/corrected annoying bug in floating point documentation of the opcode
table.
dgisselq 2470d 05h /
77 First check-in: the test bench for the divide instruction. dgisselq 2471d 04h /
76 The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions.
dgisselq 2471d 04h /
75 Modified for VLIW instructions. dgisselq 2471d 04h /
74 Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files.
dgisselq 2471d 04h /
73 Documentations updates. dgisselq 2471d 04h /
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.
dgisselq 2471d 04h /
71 This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus.
dgisselq 2471d 04h /
70 Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes.
dgisselq 2471d 05h /
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2477d 09h /
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 2512d 09h /
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 2512d 09h /
66 Adjusted the support for the DEBUG_SCOPE within these so that it can be
compiled in, or not, based upon an external build configuration file: cpudefs.v.
That allows me to make that file project specific, while the rest of the CPU
is shared among all projects.
dgisselq 2538d 09h /
65 Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any.
dgisselq 2538d 09h /
64 Shuffled some comments into here from elsewhere. dgisselq 2538d 09h /
63 Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine.
dgisselq 2538d 09h /
62 Simplified the subtraction logic, so the carry bit no longer depends on
a separate 32-bit operation but becomes part of the subtract operation.
dgisselq 2538d 09h /
61 Simplified the bus delay logic. Depends upon the stall line being irrelevant
outside of a bus cycle.
dgisselq 2538d 09h /
60 Fixed assembler processing of jump instructions, so that the new fast
return instruction can be used. The test file was modified to test
pipelined value passing within the CPU. That's where the value gets
(re)used before being stored back in the register file. As of this release,
all tests work.
dgisselq 2538d 09h /
59 Adjusted these library routines to use the new stack frame and calling
conventions.
dgisselq 2538d 09h /

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