URL https://opencores.org/ocsvn/ata/ata/trunk

Subversion Repositories ata

[/] - Rev 6

Rev 6, 2001-07-09 18:48:43 GMT
Author: rherveille
Log message:
Added 'timescale to all files
Fixed bug where control registers would always latch data, instead of when addressed

Path
/trunk/verilog/ocidec-1/ata.v
/trunk/verilog/ocidec-1/controller.v
/trunk/verilog/ocidec-1/counter.v
/trunk/verilog/ocidec-1/pio_tctrl.v