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Last modification

  • Rev 23, 2003-01-13 00:47:32 GMT
  • Author: philippe
  • Log message:
    This commit was generated by cvs2svn to compensate for changes in r22, which
    included commits to RCS files with non-trunk default branches.
Path
/trunk/impl/Xilinx_xc2s15
/trunk/impl/Xilinx_xc2s15/automake.err
/trunk/impl/Xilinx_xc2s15/automake.log
/trunk/impl/Xilinx_xc2s15/miniuart.jhd
/trunk/impl/Xilinx_xc2s15/par.opt
/trunk/impl/Xilinx_xc2s15/Rxunit.jhd
/trunk/impl/Xilinx_xc2s15/Txunit.jhd
/trunk/impl/Xilinx_xc2s15/uart.bld
/trunk/impl/Xilinx_xc2s15/uart.cup
/trunk/impl/Xilinx_xc2s15/uart.dly
/trunk/impl/Xilinx_xc2s15/uart.mrp
/trunk/impl/Xilinx_xc2s15/uart.nc1
/trunk/impl/Xilinx_xc2s15/uart.ncd
/trunk/impl/Xilinx_xc2s15/uart.ngc
/trunk/impl/Xilinx_xc2s15/uart.ngd
/trunk/impl/Xilinx_xc2s15/uart.ngm
/trunk/impl/Xilinx_xc2s15/uart.pad
/trunk/impl/Xilinx_xc2s15/uart.par
/trunk/impl/Xilinx_xc2s15/uart.pcf
/trunk/impl/Xilinx_xc2s15/uart.prj
/trunk/impl/Xilinx_xc2s15/uart.syr
/trunk/impl/Xilinx_xc2s15/uart.xpi
/trunk/impl/Xilinx_xc2s15/uart.xst
/trunk/impl/Xilinx_xc2s15/uart._prj
/trunk/impl/Xilinx_xc2s15/uart_map.ncd
/trunk/impl/Xilinx_xc2s15/uart_ngdbuild.nav
/trunk/impl/Xilinx_xc2s15/utils.jhd
/trunk/impl/Xilinx_xc2s15/xilinx.jid
/trunk/impl/Xilinx_xc2s15/Xilinx.npl
/trunk/impl/Xilinx_xc2s15/_map.log
/trunk/impl/Xilinx_xc2s15/_map.rsp
/trunk/impl/Xilinx_xc2s15/_nc1TOncd_exewrap.rsp
/trunk/impl/Xilinx_xc2s15/_ngdTOnc1_exewrap.rsp
/trunk/impl/Xilinx_xc2s15/_ngo
/trunk/impl/Xilinx_xc2s15/_ngo/netlist.lst
/trunk/impl/Xilinx_xc2s15/_par.log
/trunk/impl/Xilinx_xc2s15/_par.rsp
/trunk/impl/Xilinx_xc2s15/_prepar.rsp
/trunk/impl/Xilinx_xc2s15/__ednTOngd_exewrap.rsp
/trunk/impl/Xilinx_xc2s15/__launchTA.tcl
/trunk/impl/Xilinx_xc2s15/__ngdbuild.rsp
/trunk/impl/Xilinx_xc2s15/__projnav.log
/trunk/impl/Xilinx_xc2s15/__uart_2prj_exewrap.rsp
/trunk/impl/Xilinx_xcs10/Xilinx/xilinx/chips
/trunk/impl/Xilinx_xcs10/Xilinx/xilinx/chips/ver1
/trunk/impl/Xilinx_xcs10/Xilinx/xilinx/chips/ver1-Optimized
/trunk/impl/Xilinx_xcs10/Xilinx/xilinx/chips/ver1-Optimized/ver1-Optimized.cst
/trunk/impl/Xilinx_xcs10/Xilinx/xilinx/chips/ver1-Optimized/ver1-Optimized.rpt
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/trunk/impl/Xilinx_xcs10/Xilinx/xilinx/workdirs/WORK/UART.hnl
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/trunk/sim/Foundation sim/testrx.pdf
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/trunk/sim/ModelSim
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