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[/] - Rev 180

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Last modification

  • Rev 180, 2013-02-25 21:23:18 GMT
  • Author: olivier.girard
  • Log message:
    Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
    Thanks to Sebastien Van Cauwenberghe's contribution :-)
Path
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v
/openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v

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