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[/] - Rev 30

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Last modification

  • Rev 30, 2009-12-27 21:02:43 GMT
  • Author: olivier.girard
  • Log message:
    Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution).
Path
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v

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