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Subversion Repositories openmsp430

[/] - Rev 39

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Last modification

  • Rev 39, 2009-12-29 21:38:00 GMT
  • Author: olivier.girard
  • Log message:
    Update FPGA projects with new openMSP430 core.
Path
/openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v
/openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/alu.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/clock_module.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_hwbrk.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_uart.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/execution_unit.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/frontend.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/mem_backbone.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/gpio.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/timerA.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/register_file.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/sfr.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/watchdog.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/rom16x2048.v
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/pmem.elf
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/pmem.ihex
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/pmem.inc
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/pmem.mem

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