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Last modification

  • Rev 627, 2011-08-24 03:28:01 GMT
  • Author: stekern
  • Log message:
    orpsoc: add Digilent Atlys spartan6 board rtl

    Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Path
/openrisc/trunk/orpsocv2/boards/xilinx/atlys
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_bytebus.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_dbus.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_ibus.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen/clkgen.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/README
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_cpu_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_wb_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/i2c_master_slave_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-params.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/tap_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/uart_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/xilinx_ddr2_params.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr/lfsr.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/ddr2_mig.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/infrastructure.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/README
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v

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