URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 63, 2010-01-10 12:31:11 GMT
• Author: julius

• Log message:

  Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.

Path
/openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h
/openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h
/openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h
/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
/openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h
/openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h
/openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h
/openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h
/openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make
/openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sw/utils/binlog2readable.cpp
/openrisc/trunk/orpsocv2/sw/utils/Makefile