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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] - Rev 12

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Last modification

  • Rev 12, 2009-11-26 11:05:27 GMT
  • Author: xianfeng
  • Log message:
    check-in SoC source
Path
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/DataFlash_Verilog_manual.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/AT26DFxxx.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/filelist.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/memory.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/run.csh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/testbench_AT26DFx.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/top26x_testbench.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/bench_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/CPUboard_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/generic_pll
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/generic_pll/generic_pll.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/28f016s3.bkb
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/28f016s3.bke
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/bwsvff.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/dp016s3.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/read.me
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/test1s3.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/test_bad.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/256Kx16.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/512Kx8.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/codec_model.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/idt71256sa15.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/vga_model.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/ddr.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/ddr_dimm.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/ddr_parameters.vh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/readme.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/subtest.vh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/tb.do
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/mt48lc16m16a2.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/s25fl032a.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/s25fl128p01m.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/altera_ram.vwf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/altera_ram_top.vwf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/altera_ram_top_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/bootrom
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/bootrom/boot.mif
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/build.sh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/download_image.sh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/or1k_soc_top.vwf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/or1k_soc_top_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/README
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/reset_jtag.sh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/setup_prj.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/README
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl/vhdl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/BSDL
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/BSDL/opencores_tap.bsd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog/BiDirectionalCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog/ControlCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog/InputCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog/OutputCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/gpl-2.0.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/jtag.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/src/jtag.odt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/src/oc_jtag_sys_diag.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/src/system_block_diagram.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/rtl/verilog
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/rtl/verilog/tap_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/xilinx_internal_jtag
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.html
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.ppf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.qip
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_advisor.ipa
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy.v
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.v
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll_bb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll_inst.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq.vhd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.vo
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_bb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_ddr_pins.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_ddr_timing.sdc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_report_timing.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_pin_assignments.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_syn.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altmemphy-library
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/ddr_high_performance_controller-library
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/ddr_high_performance_controller-library/auk_ddr_hp_controller.ocp
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_inst.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_syn.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_wave0.jpg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_waveforms.html
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram
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