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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] - Rev 12

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Last modification

  • Rev 12, 2009-11-26 11:05:27 GMT
  • Author: xianfeng
  • Log message:
    check-in SoC source
Path
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/DataFlash_Verilog_manual.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/AT26DFxxx.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/filelist.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/memory.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/run.csh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/testbench_AT26DFx.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/top26x_testbench.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/bench_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/CPUboard_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/generic_pll
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/generic_pll/generic_pll.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/28f016s3.bkb
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/28f016s3.bke
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/bwsvff.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/dp016s3.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/read.me
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/test1s3.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/28f016s3/test_bad.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/256Kx16.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/512Kx8.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/codec_model.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/idt71256sa15.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/models/vga_model.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/ddr.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/ddr_dimm.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/ddr_parameters.vh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/readme.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/subtest.vh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/tb.do
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/MT46V16M16/tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/mt48lc16m16a2.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/s25fl032a.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/bench/s25fl128p01m.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/altera_ram.vwf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/altera_ram_top.vwf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/altera_ram_top_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/bootrom
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/bootrom/boot.mif
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/build.sh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/download_image.sh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/or1k_soc_top.vwf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/or1k_soc_top_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/README
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/reset_jtag.sh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/setup_prj.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/README
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl/vhdl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/BSDL
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/BSDL/opencores_tap.bsd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog/BiDirectionalCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog/ControlCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog/InputCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/cells/rtl/verilog/OutputCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/gpl-2.0.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/jtag.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/src/jtag.odt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/src/oc_jtag_sys_diag.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/doc/src/system_block_diagram.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/rtl/verilog/tap_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/jtag/tap/rtl/verilog/tap_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/xilinx_internal_jtag
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/xilinx_internal_jtag/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/xilinx_internal_jtag/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag_options.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.bsf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.html
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.ppf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.qip
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_advisor.ipa
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_auk_ddr_hp_controller_wrapper.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_auk_ddr_hp_controller_wrapper.vo
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_bb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_controller_phy.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_example_driver.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_example_top.sdc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_example_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_ex_lfsr8.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy.bsf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy.html
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy.qip
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.qip
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.v_.bak
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll_bb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll_inst.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq.vhd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.vo
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_bb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_ddr_pins.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_ddr_timing.sdc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_phy_report_timing.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_pin_assignments.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_syn.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altera_ddr_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altmemphy-library
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/altmemphy-library/auk_ddr_hp_controller.ocp
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/alt_mem_phy_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/auk_ddr_hp_controller.ocp
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/auk_ddr_hp_controller.vhd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/ddr_high_performance_controller-library
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/ddr_high_performance_controller-library/auk_ddr_hp_controller.ocp
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/testbench
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/testbench/altera_ddr_example_top_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/testbench/altera_ddr_full_mem_model.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ddr_ctrl/testbench/altera_ddr_mem_model.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll.bsf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll.ppf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll.qip
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_bb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_inst.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_syn.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_wave0.jpg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_pll/altera_pll_waveforms.html
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram.bsf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram.qip
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram_bb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram_inst.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram_syn.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram_wave0.jpg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram_wave1.jpg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram_wave2.jpg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/altera_ram_waveforms.html
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/altera_ram/timescale.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/README.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_cpu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_cpu_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_cpu_registers.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_crc32_d1.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_register.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_wb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/dbg_interface/rtl/verilog/dbg_wb_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/BUGS
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_clockgen.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_cop.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_crc.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_fifo.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_maccontrol.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_macstatus.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_miim.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_outputcontrol.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_random.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_receivecontrol.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_register.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_registers.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_rxaddrcheck.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_rxcounters.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_rxethmac.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_rxstatem.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_shiftreg.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_spram_256x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_transmitcontrol.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_txcounters.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_txethmac.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_txstatem.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/eth_wishbone.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/timescale.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/TODO
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/ethernet/rtl/verilog/xilinx_dist_ram_16x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/flash_sram
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/flash_sram/flash_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/flash_sram/sram_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/flash_sram/sram_top.v.orig
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/gpio
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/gpio/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/gpio/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/gpio/rtl/verilog/gpio_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/gpio/rtl/verilog/gpio_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_adr_sel.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_cs_rf.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_dp.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_incn_r.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_mem_if.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_obct.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_obct_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_rd_fifo.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_refresh.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_rf.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_timing.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mem_if/rtl/verilog/mc_wb_if.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/ctrlStsRegBI.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/initSD.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/readWriteSDBlock.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/readWriteSPIWireData.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/sendCmd.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/sm_dpMem_dc.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/sm_fifoRTL.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/sm_RxFifo.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/sm_RxFifoBI.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/sm_TxFifo.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/sm_TxFifoBI.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/spiCtrl.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/spiMaster.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/spiMasterWishBoneBI.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/spiMaster_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/spiTxRxData.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/mmc_sd/RTL/timescale.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1k_soc_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1k_soc_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_alu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_amultp2_32x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_cfgr.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_cpu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_ctrl.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_dc_fsm.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_dc_ram.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_dc_tag.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_dc_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_dmmu_tlb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_dmmu_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_dpram_32x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_dpram_256x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_du.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_except.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_freeze.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_genpc.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_ic_fsm.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_ic_ram.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_ic_tag.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_ic_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_if.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_immu_tlb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_immu_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_iwb_biu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_lsu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_mem2reg.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_mult_mac.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_operandmuxes.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_pic.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_pm.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_qmem_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_reg2mem.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_rf.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_rfram_generic.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_sb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_sb_fifo.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_32x24.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_64x14.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_64x22.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_64x24.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_128x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_256x21.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_512x20.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_1024x8.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_1024x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_2048x8.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_2048x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_sprs.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_tpram_32x32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_tt.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_wbmux.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_wb_biu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/or1200/rtl/verilog/timescale.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/rom_wb
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/rom_wb/rom_wb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/spi
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/spi/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/spi/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/spi/rtl/verilog/spi_clgen.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/spi/rtl/verilog/spi_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/spi/rtl/verilog/spi_shift.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/spi/rtl/verilog/spi_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/spi/rtl/verilog/timescale.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup/timescale.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup/uart_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup/uart_fifo.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup/uart_receiver.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup/uart_regs.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup/uart_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup/uart_transmitter.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog-backup/uart_wb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/raminfr.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/timescale.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_debug_if.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_receiver.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_regs.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_rfifo.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_sync_flops.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_tfifo.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_transmitter.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/verilog/uart_wb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/vhdl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/uart16550/rtl/vhdl/.keepme
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_arb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_master_if.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_msel.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_rf.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/wb_conmax/rtl/verilog/wb_conmax_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/bin
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/bin/iver.cmd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/bin/iver.cmd.all
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/bin/iver.cmd.new
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/bin/Makefile
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/bin/wave_signals.sav
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/run
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sim/src/create_flash.sh
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/adv_dbg_commands.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/adv_dbg_commands.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/adv_jtag_bridge.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/adv_jtag_bridge.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/altera_virtual_jtag.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/bsdl.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/bsdl.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/bsdl_parse.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/bsdl_parse.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_common.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_common.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_ft2232.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_ft2232.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_parallel.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_parallel.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_sim.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_sim.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_usbblaster.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_usbblaster.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_xpc_dlc9.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_xpc_dlc9.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/chain_commands.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/chain_commands.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/dbg_api.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/dbg_api.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc/adv_jtag_bridge.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc/gpl-2.0.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc/License_FDL-1.2.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc/src/adv_jtag_bridge.odt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc/src/ajb_block_diagram.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/errcodes.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/errcodes.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/except.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/gdb-6.8-bz436037-reg-no-longer-active.patch
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/legacy_dbg_commands.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/legacy_dbg_commands.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/Makefile
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/opencores_tap.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/or32_selftest.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/or32_selftest.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/README
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/rsp-server.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/rsp-server.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_lib
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_lib/icarus/Makefile
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_lib/modelsim_linux_x86
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_lib/modelsim_win32
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/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_lib/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_lib/src/jp-io-vpi.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_rtl/dbg_comm.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_rtl/dbg_comm_vpi.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/spr-defs.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader/board.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader/BootReset.S
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader/main.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader/Makefile
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader/orsocdef.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader/ram.ld
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader/revision.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/sd_boot_loader/spr_defs.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/toolchain
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/toolchain/Makefile
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/toolchain/README
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/utils
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/utils/gen_memory_text.pl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/utils/gen_memory_text_spi_flash.pl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/utils/gen_verilog_mem_block.pl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/utils/hex2mif.pl
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