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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

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Last modification

  • Rev 21, 2010-01-18 16:20:37 GMT
  • Author: xianfeng
  • Log message:
    merge adv_debug_sys r33 that adds high_speed and with my ftdi
Path
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/prj/altera/setup_prj.tcl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/wave.do
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/xsv_fpga_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/xsv_fpga_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/README_testbench.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/cpu_behavioral.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/timescale.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/wave.do
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/wb_model_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/wb_slave_behavioral.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc/AdvancedDebugInterface.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc/gpl-2.0.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc/License_FDL-1.2.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc/src/AdvancedDebugInterface.odt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc/src/generic_submodule.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc/src/system_block_diagram.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/doc/src/top_level_module.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/doc/altera_virtual_jtag.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/doc/gpl-2.0.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/doc/License_FDL-1.2.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/doc/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/doc/src/altera_virtual_jtag.odt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/BSDL
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/BSDL/opencores_tap.bsd
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/cells
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/cells/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/cells/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/cells/rtl/verilog/BiDirectionalCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/cells/rtl/verilog/ControlCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/cells/rtl/verilog/InputCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/cells/rtl/verilog/OutputCell.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/doc/gpl-2.0.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/doc/jtag.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/doc/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/doc/src/jtag.odt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/doc/src/oc_jtag_sys_diag.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/doc/src/system_block_diagram.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/doc
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/gpl-2.0.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/License_FDL-1.2.txt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/src
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/src/xilinx_bscan_waveform.odg
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/src/xilinx_internal_jtag.odt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/xilinx_internal_jtag.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/rtl
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/rtl/verilog
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag_options.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/rtl/adv_debug_sys/tags
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/adv_dbg_commands.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/adv_jtag_bridge.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/adv_jtag_bridge.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/bsdl.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/bsdl_parse.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_common.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_usbblaster.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_usbblaster.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_usbblaster_ftdi.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/cable_xpc_dlc9.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/chain_commands.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/chain_commands.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/dbg_api.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc/adv_jtag_bridge.pdf
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/doc/src/adv_jtag_bridge.odt
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/errcodes.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/legacy_dbg_commands.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/Makefile
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/or32_selftest.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/or32_selftest.h
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/rsp-server.c
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_lib/Makefile
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_rtl/dbg_comm.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/adv_jtag_bridge/sim_rtl/dbg_comm_vpi.v
/or1k_soc_on_altera_embedded_dev_kit/trunk/soc/sw/orpmon/include/board.h

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