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Last modification

• Rev 5, 2006-03-30 02:47:07 GMT
• Author: rudi

• Log message:

  Thanks to Darren O'Connor of SPEC, Inc. for fixing a bug
  with the DPLL and data alignment:
  
  You were right that it was a problem with the dpll. I found
  that it was possible to get two baud clocks (rx_sio_ce) during
  one bit period. I fixed the problem by delaying the input data
  signal with a shift register and using that in the equations
  for the "change" variable that controls the DPLL FSM.