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[/] - Rev 10
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Last modification
- Rev 10, 2016-10-15 17:00:29 GMT
- Author: jdoin
- Log message:
- Optimized control logic;
Reduced one clock cycle for full last blocks, eliminated sch_ld redundant logic.
Improved error detection logic, eliminating the bytes error register.
Updated testbench with write violations and full block corner case tests.