URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] - Rev 102

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Last modification

Rev 102, 2011-12-13 05:14:31 GMT
Author: jt_eaton
Log message:
all ip-xact files now readable by kactus2

Path
/socgen/trunk/Makefile
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/busdeftypes/clock.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/rtl/xml/clock.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/busdeftypes/enable.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/rtl/xml/enable.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/busdeftypes/micro_bus.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/rtl/xml/ext_bus.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/jtag/busdeftypes/jtag.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/jtag/rtl/xml/jtag_rpc.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/jtag/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/busdeftypes/micro_bus.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/rtl/xml/micro_bus.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/busdeftypes/pad.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/rtl/xml/pad.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/busdeftypes/ps2.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/rtl/xml/ps2.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/busdeftypes/reset.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/rtl/xml/reset.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/busdeftypes/uart.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/rtl/xml/uart.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/busdeftypes/vga.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/rtl/xml/vga.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/soc
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone/busdeftypes/wishbone.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone/rtl/xml/wishbone.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/sim/cde_divider.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/syn/cde_divider.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/xml/cde_divider.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/verilog/cde_fifo.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_io_mux
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/sim/cde_lifo.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/syn/cde_lifo.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/sim/cde_sram.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/syn/cde_sram.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Basys_mrisc
/socgen/trunk/projects/opencores.org/fpgas/ip/Basys_soc_mrisc
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_soc_mrisc
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_def.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_def.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_tb.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_def.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_def.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_default.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/xml/Basys_mrisc_tb.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/xml/Basys_mrisc_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_default.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_mouse.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_tb.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_default.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_tb.design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/x
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/xml/io_ext_mem_interface_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/xml/io_ext_mem_interface_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/xml/io_gpio_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/xml/io_gpio_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_gpio_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_gpio_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_mouse_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_mouse_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/xml/io_pic_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/xml/io_pic_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_mouse_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_mouse_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/xml/io_timer.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/xml/io_timer_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/xml/io_timer_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/xml/io_timer_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/xml/io_timer_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rxtx_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rxtx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rx_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tx_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/xml/io_utimer.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/xml/io_utimer_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/xml/io_utimer_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/xml/io_utimer_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/xml/io_utimer_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/xml/io_vga_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/xml/io_vga_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/xml/io_vic.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/xml/io_vic_def.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/xml/io_vic_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/xml/io_vic_tb.design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/xml/io_vic_tb.xml
/socgen/trunk/projects/opencores.org/io/soc
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/rtl/xml/disp_io.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/rtl/xml/usb_epp.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_def.design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_def.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/sim/verilog/tb.ext_m
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/sim/xml/T6502_tb.design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/sim/xml/T6502_tb.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu_def.design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu_def.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/sim/xml/T6502_cpu_tb.design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/sim/xml/T6502_cpu_tb.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic_def.design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic_def.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/sim/verilog/tb.ext
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/sim/xml/T6502_cpu_alu_logic_tb.design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/sim/xml/T6502_cpu_alu_logic_tb.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc/rtl/xml/mrisc_def.design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc/rtl/xml/mrisc_def.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc/sim/xml/mrisc_tb.design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc/sim/xml/mrisc_tb.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/rtl/verilog/register_file
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_def.design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_def.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_io_tb.design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_io_tb.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_tb.design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_tb.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/rtl/xml/soc_mrisc_io.design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/rtl/xml/soc_mrisc_io.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/verilog/top.ext.mouse
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/verilog/top.ext.mouse_mrisc
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/xml/soc_mrisc_io_tb.design.xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/xml/soc_mrisc_io_tb.xml
/socgen/trunk/projects/opencores.org/targets/ip/Basys/lib/ip/cde_jtag/rtl/views/syn/cde_jtag.v
/socgen/trunk/projects/opencores.org/targets/ip/Nexys2/lib/ip/cde_jtag/rtl/views/syn/cde_jtag.v
/socgen/trunk/projects/opencores.org/Testbench/ip/clock_gen/rtl/views/sim/clock_gen.v
/socgen/trunk/projects/opencores.org/Testbench/ip/clock_gen/rtl/views/syn/clock_gen.v
/socgen/trunk/projects/opencores.org/Testbench/ip/clock_gen/rtl/xml/clock_gen.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/gpio_model
/socgen/trunk/projects/opencores.org/Testbench/ip/io_probe/rtl/xml/io_probe.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/jtag_model/rtl/xml/jtag_model.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus16_model/rtl/xml/micro_bus16_model.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/micro_bus_model/rtl/xml/micro_bus_model.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/mt45w8mw12/rtl/xml/mt45w8mw12.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_host/rtl/xml/ps2_host.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/ps2_model/rtl/xml/ps2_model.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_host/rtl/xml/uart_host.xml
/socgen/trunk/projects/opencores.org/Testbench/ip/uart_model/rtl/xml/uart_model.xml

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