OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 105

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 105, 2012-03-06 01:48:34 GMT
  • Author: jt_eaton
  • Log message:
    moved or1200_monitor from testbench to dut
Path
/socgen/trunk/projects/opencores.org/orp_soc/doc/pdf/case_or1k.pdf
/socgen/trunk/projects/opencores.org/orp_soc/doc/pdf/journal.pdf
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/case_or1k.html
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/journal.html
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/arbiter/arbiter.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_cpu_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_register.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/dbg_wb_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/jtag_tap/tap_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_monitor.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/timescale.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200/wb_checker.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/or1200_monitor_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/orpsoc-params.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/ram_wb/ram_wb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/tap_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/test-defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/top.or1200_mon
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/raminfr.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_debug_if.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_receiver.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_regs.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_rfifo.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_tfifo.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_transmitter.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart16550/uart_wb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/uart_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/xml/generic_orpsocv2_ra_ti_ua.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-basic/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/uart-interruptloopback/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/uart-interruptloopback/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/uart-simple/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/uart-simple/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/xml/generic_orpsocv2_ra_ti_ua_tb.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/xml/generic_orpsocv2_ra_ti_ua_tb.xml

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.