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[/] - Rev 110

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Last modification

  • Rev 110, 2012-03-18 23:50:57 GMT
  • Author: jt_eaton
  • Log message:
    split out more ip-xact components
    added sw sources
Path
/socgen/trunk/projects/opencores.org/orp_soc/bin/compile
/socgen/trunk/projects/opencores.org/orp_soc/bin/Makefile.or32
/socgen/trunk/projects/opencores.org/orp_soc/doc/src/journal.html
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/doc
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/doc/copyright.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/ip-xact
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/ip-xact/adv_dbg_if_wb_cpu.designCfg.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_crc32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_jsp_module.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/adbg_wb_module.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/bytefifo.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/syncflop.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/verilog/syncreg.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/sim
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/sim/bin
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/doc
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/doc/copyright.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/ip-xact
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/rtl/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/rtl/verilog/README
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/rtl/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/rtl/xml/clkgen_def.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/sim
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/sim/bin
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/doc
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/doc/copyright.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/ip-xact
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_cpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_cpu_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_cpu_registers.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_crc32_d1.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_register.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_wb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/dbg_wb_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/verilog/timescale.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/xml/dbg_if_wb_cpu.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/sim
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/sim/bin
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/xml/generic_orpsocv2_ra_ti_ua.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/xml/generic_orpsocv2_ra_ti_ua.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag-basic/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/jtag-basic/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/icarus/or1200-except/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/xml/generic_orpsocv2_ra_ti_ua_tb.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/sim/xml/generic_orpsocv2_ra_ti_ua_tb.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/doc
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/doc/copyright.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/ip-xact
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/rtl/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/rtl/verilog/tap_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/rtl/verilog/tap_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/rtl/verilog/timescale.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/rtl/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/rtl/xml/jtag_tap.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/sim
/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/sim/bin
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/rtl/xml/Nexys2_orpsocv2_default.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/Nexys2_orpsocv2/sim/icarus/uart-simple/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/bin
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/doc
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/doc/copyright.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/ip-xact
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/ip-xact/or1200_dbg.designCfg.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_alu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_amultp2_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_cfgr.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_cpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_ctrl.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dc_fsm.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dc_ram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dc_tag.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dc_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dmmu_tlb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dmmu_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dpram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dpram_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_dpram_256x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_du.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_except.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_addsub.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_arith.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_div.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_fcmp.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_mul.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_post_norm_addsub.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_post_norm_div.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_post_norm_mul.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_pre_norm_addsub.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_pre_norm_div.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_fpu_pre_norm_mul.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_freeze.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_genpc.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_ic_fsm.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_ic_ram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_ic_tag.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_ic_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_if.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_immu_tlb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_immu_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_iwb_biu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_lsu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_mem2reg.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_monitor.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_monitor_defines.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_mult_mac.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_operandmuxes.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_pic.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_pm.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_qmem_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_reg2mem.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_rf.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_rfram_generic.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_sb.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_sb_fifo.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_32x24.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_32_bw.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_64x14.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_64x22.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_64x24.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_128x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_256x21.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_512x20.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_1024x8.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_1024x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_2048x8.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_2048x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_sprs.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_top.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_tpram_32x32.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_tt.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_wbmux.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_wb_biu.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/synthesys
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/timescale.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/top.or1200_mon
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/verilog/wb_checker.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/xml/or1200_dbg.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim
/socgen/trunk/projects/opencores.org/orp_soc/ip/or1200/sim/bin
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/orpsoc-params.v
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/verilog/top.rtl
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/xml/orpsocv2_ra_ti_ua.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/rtl/xml/orpsocv2_ra_ti_ua.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/icarus/or1200-pm
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/icarus/or1200-pm/dmp_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/icarus/or1200-pm/test_define
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/icarus/or1200-pm/wave.sav
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/xml/orpsocv2_ra_ti_ua_tb.design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/orpsocv2/sim/xml/orpsocv2_ra_ti_ua_tb.xml
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/board.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/cpu-utils.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/int.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/lib-utils.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/link.ld
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/or1200-defines.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/or1200-utils.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/orpsoc-defines.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/printf.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/spr-defs.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/backend/uart.h
/socgen/trunk/projects/opencores.org/orp_soc/sw/cache
/socgen/trunk/projects/opencores.org/orp_soc/sw/cache/cache.S
/socgen/trunk/projects/opencores.org/orp_soc/sw/cache/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/sw/crt0
/socgen/trunk/projects/opencores.org/orp_soc/sw/crt0/crt0.S
/socgen/trunk/projects/opencores.org/orp_soc/sw/crt0/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/sw/exceptions
/socgen/trunk/projects/opencores.org/orp_soc/sw/exceptions/exceptions.c
/socgen/trunk/projects/opencores.org/orp_soc/sw/exceptions/Makefile
/socgen/trunk/projects/opencores.org/orp_soc/sw/int
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/socgen/trunk/projects/opencores.org/Testbench/ip/jtag_model/rtl/verilog/top.tasks
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